I gave an AI a real FPGA bug and watched it put a probe on every pipeline stage.
From the first step it scanned stage by stage, and locked the bug on its own.
No guessing. Here is how it worked.
The decoder passed everything. Zero bit errors. The Python cycle model and the hardware matched bit-for-bit at the output. Simulation passed. Place-and-route passed. All green.
One small thing was off. For the same input, the model took 8 rounds to converge. The hardware took 7. Same answer, different path.
Easy to wave away.