# I gave an AI a real FPGA bug and watched it put a probe on every pipeline sta...
Canonical: https://social-archive.org/fathul/09mLgHC4DE
Original URL: https://www.linkedin.com/feed/update/urn:li:activity:7462888998315802624/
Author: Jie LEI
Platform: linkedin
## Content
I gave an AI a real FPGA bug and watched it put a probe on every pipeline stage. From the first step it scanned stage by stage, and locked the bug on its own. No guessing. Here is how it worked. The decoder passed everything. Zero bit errors. The Python cycle model and the hardware matched bit-for-bit at the output. Simulation passed. Place-and-route passed. All green. One small thing was off. For the same input, the model took 8 rounds to converge. The hardware took 7. Same answer, different path. Easy to wave away. But the model is the golden reference the hardware gets checked against. If the two disagree, which one do you trust? Here is the part people assume an AI cannot do: it did not start twiddling parameters. It instrumented the decode. A probe on the internal state after every step, both versions running in lockstep, scanned from the very first step, stopping the instant they disagreed. It locked onto one spot: decode layer 8. Everything before it matched; everything after was just downstream fallout. The cause was small. A cyclic shifter needs its data and its rotation amount on the same clock cycle. The data travels through a 3-stage pipeline to get there. The rotation amount did not, so it arrived 3 cycles too early and got paired with the wrong data. The algorithm self-corrects, so it still decoded perfectly. It just burned one extra round cleaning up the mismatch. That is exactly why every output test passed and the bug stayed invisible. The fix was one line: delay the rotation so it lines up with the data. The lesson I keep relearning: do not guess at a bug. Probe every stage, scan from the start, and let the first divergence point straight at the cause. The AI did that without being told. What part of your hardware debug flow would you most want an agent to take over? #FPGA #AI #HardwareDesign #LDPC #Debugging